Tuesday, February 18, 2003

InnoLogic Systems Tools Validate Functional Models for STMicroelectronics Embedded Memories

ESP-CV Provides Complete Functional Coverage and Streamlines the Verification Flow for 90 Nanometer Memories

SAN JOSE, Calif.--Feb. 18, 2003-- InnoLogic Systems, Inc., a provider of functional verification solutions for full custom silicon design implementations, today announced a major customer win from STMicroelectronics (NYSE:STM - News), one of the world's largest semiconductor companies and a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. STMicroelectronics' Central R&D division is using InnoLogic's ESP-CV to eliminate functional bugs in its embedded memories that are included in major product lines such as telecom and data communications and consumer and automotive electronics.

Dian Yang, president and CEO of InnoLogic, noted, "A leading semiconductor company like STMicroelectronics needs the confidence that they are delivering high-quality products to the market. ESP-CV enables designers to achieve complete functional verification coverage of embedded memories -- something that they have not been able to accomplish using mainstream verification solutions."

"As designs move toward 90 nanometers and below, we see increasing verification challenges for full custom silicon elements, such as embedded memories that occupy a growing portion of SOC designs," added Yang. "Adding ESP-CV to the design flow saves significant engineering time and gives customers the confidence that their product will work as designed and verified."

Philippe Magarshack, Group Vice President of Central R&D, Design Automation for STMicroelectronics explained, "The families of SRAMs and ROMs generated by our memory compilers as well as embedded DRAMs are found in just about every significant microelectronics product that we manufacture. The presence of even one functional bug in these embedded memories could have a significant impact on our business. Before we had ESP-CV, we had to verify the HDL models and SPICE circuits separately using traditional simulation, which not only was incomplete, but also consumed significantly more internal resources."

Magarshack continued, "InnoLogic's ESP-CV has enabled us to implement an automated flow to directly verify the functional equivalence of dozens of HDL models and SPICE netlists created by our memory compiler. This significantly enhanced our overall design quality and productivity."

Instead of requiring manual translation of a SPICE netlist to a Verilog gate-level netlist, which can be time-consuming and error prone, ESP-CV automatically reads the SPICE netlist and its parasitic information for equivalency checking. With ESP-CV, STMicroelectronics was able to find and fix functional bugs like incorrect data storage handling of their highly complex SRAM models with aggressive pre-charge techniques. By streamlining the verification process of compiler generated embedded SRAM's, ROM's and DRAM's, STMicroelectronics expects to increase the quality of their embedded memories and get their silicon to market faster.


About ESP-CV

InnoLogic Systems' ESP-CV product verifies the functional equivalency of full custom designs across various levels of abstraction. The design representations may be in Verilog behavioral, RTL, UDPs, gates, transistor-level or SPICE netlist. If a difference is found during the equivalence checking process, ESP-CV produces a shallow set of binary vectors that depicts the differences. These vectors can then be used directly in the existing simulation environment during the debug process to determine the root cause of the difference. ESP-CV provides transistor-level accuracy by automatically modeling parasitic effects using an RC model based on the transistor length, width, and process technology.


About InnoLogic Systems, Inc.

InnoLogic Systems, Inc. helps engineers gain confidence in the quality of their designs and reduces the overall verification cost by offering functional verification solutions for full custom silicon implementations. Based on patented symbolic simulation and transistor-level formal analysis technologies, InnoLogic's products provide complete functional verification coverage with accurate representation of circuit-level characteristics for full custom design blocks contained within high performance SOC designs. The San Jose-based company has customers throughout the world in major market segments including semiconductor, microprocessor, and networking. For additional information, visit www.innologic-systems.com or call (408)432-6188.


Source: InnoLogic Systems, Inc.